In recent years, a nonvolatile semiconductor memory device equipped with a nonvolatile semiconductor memory has been required to be equipped with a large-capacity nonvolatile semiconductor memory with the increase of the variety of applications and the like.
One of the factors hindering the increase of the capacity of a nonvolatile semiconductor memory is the increase of the chip cost caused by the increase of the area of a chip. In this light, proposed are: a Single MONOS (Metal Oxide Nitride Oxide Semiconductor) memory having the configuration of one transistor to one bit as described in JP-A No. 77197/1986 in order to reduce a chip area; and also a charge pump circuit to generate high voltage corresponding to the Single MONOS (hereunder referred to as “S-MONOS).
FIGS. 1A to 1D are diagrams showing operation biases in the various modes of an S-MONOS. As shown in FIG. 1A, at the time of erase, the threshold value (Vth) of a memory cell is set to the negative side by: applying −8.5 V to a memory gate (MG) and 1.5 V which is the power supply voltage to a well, a source (S), and a drain (D); and extracting electrons in a nitride film to the side of the well by the tunnel effect. As shown in FIG. 1B, at the time of write, the threshold value (Vth) of a memory cell is set to the positive side by: applying 1.5 V to an MG and −10.5 V to a well, a source (S), and a drain (D); and injecting electrons into a nitride film by the tunnel effect. As shown in FIG. 1C, at the time of read, by applying 0 V to a selected MG, 0 V to a source, and precharged 1.0 V to a drain: if a memory cell is in the state of erase, since Vth is negative, electric current flows between the drain and the source and thus it is detected that the drain potential lowers; and, if the memory cell is in the state of write, since Vth is positive, electric current does not flow between the drain and the source and thus it is detected that the drain potential is kept at 1 V. Further, as shown in FIG. 1D, at the time of standby, −1.5 V, which is not more than the Vth of a memory cell at the time of erase, is applied to an MG and a well.
Then, FIG. 2A shows a schematic diagram of charge pump circuits corresponding to the S-MONOS and FIG. 2B shows the charge pump circuit of each stage. In FIG. 2A, the signals CONTIN, CONTOUT, ACLK, and BCLK shown in FIG. 2B are not written for simplification. As it is obvious from the operation biases sown in FIG. 1, the feature of the configuration is that, in the charge pump circuit configuration shown in FIG. 2A, a switch is introduced between adjacent two stages of the charge pumps so as to be able to change the number of the stages of the charge pumps since the charge pump output voltage varies for each of erase/write, read, and standby.